This invention relates to circuits for rendering a service enable signal to be assigned, in accordance with a predetermined priority, to ones of a plurality of subsystems in a system, for instance a multi-processor system, in response to service request signals from the given subsystems.
Hitherto, priority assignment circuits have been used for multi-processor systems and the like. FIG. 1 shows an example of the prior art multi-processor system. This multi-processor system comprises a system memory 1, a plurality of subsystems 2-1, 2-2, . . . , 2-n, each including a central processing unit (CPU) and a local memory, and a priority assignment circuit 3. The individual subsystems 2-1, 2-2, . . . , 2-n send respective bus requests 4-1, 4-2, . . . , 4-n as service request signals to the priority assignment circuit 3 when it is necessary to access the system memory 1 for reading or writing data. The priority assignment circuit 3 sends a service enable signal or grant signal to the individual subsystems 2-1, 2-2, . . . , 2-n in accordance with a predetermined priority.
When the service enable signal, for instance signal 5-1, is given to the subsystem 2-1, the subsystem 2-1 sends an address signal through an address bus 6 to the system memory 1, while at the same time it sends a read or write signal to a control bus 7. In case of writing data, the data to be written is sent through the data bus 8 to the system memory 1, while in the case of reading data, the desired data read out from the system memory 1 is received through the data bus 8.
If the subsystem 2-1, to which the first priority is assigned, is not providing a service request signal, the service enable signal is transmitted through a service enable signal transmission unit in the priority assignment circuit 3 to the next priority subsystem 2-2 as grant signal 5-2.
FIG. 2 shows one example of the construction of the conventional priority assignment circuit 3. This circuit is disclosed as "serial priority technique" in FIG. 8 of Intel APPLICATION NOTE AP-28A, January, 1979, page 10. In FIG. 2, the priority level is highest for the service enable signal transmission unit 11-1 at the left hand end and decreases for following units 11-2, 11-3, . . . toward the right hand. To the individual units 11-1, 11-2, . . . respective priority signals 12-1, 12-2 . . . representing the priority level and service request signals 13-1, 13-2, . . . are supplied. When the service enable signal 14-1 is coupled to the unit 11-1 of the highest priority, the unit 11-1 feeds a service enable signal of the next highest priority to the next unit 11-2 depending upon the contents of the priority signal 12-1 and service request signal 13-1. Likewise, service enable signals 14-3, 14-4, . . . of progressively lower priority are fed to the following units 11-3, 11-4, . . . from their preceding units. For example, when the priority signal 12-1 becomes "1", the service enable signal 14-2 also becomes "1" to assign the highest priority to the service request signal 13-2.
The service enable signal transmission units 11-1, 11-2, . . . which produce successive service enable signals each has a construction as shown in FIG. 3, having two NAND gate stages 21 and 22 with respect to a single service request signal line. In FIG. 3, the unit 11-1 is shown as an example. Here, the service enable signal 14-1 and an inverted service request signal 13-1 are coupled to the input side of the first NAND gate stage 21, and the output signal therefrom and an inverted priority signal 12-1 are coupled to the input side of the second NAND gate stage 22. The operation of the NAND gates 21 and 22 is well known and is not described.
With the prior art priority assignment circuit as described above, a service enable signal is produced for each service request signal line. Therefore, the period required for the transmission of the service enable signal is increased in proportion to the number of the service request signal lines. For example, where there are 16 service request signal lines, a delay time of (16-1).times.2Td is the greatest delay involved in the transmission of the service enable signal. If Td, which is the delay time per NAND gate stage, is =9.5 nsec., the greatest delay time in the transmission of the service enable signal is EQU (16-1).times.2.times.9.5 nsec.=285 nsec.
It will thus be seen that as the number of service request signal lines are increased, the efficiency of the service processing is reduced.
An object of the invention, accordingly, is to provide a priority assignment circuit which can minimize the delay due to the service enable signal transmission and permit execution of the assignment of the priority with respect to a large number of service requests in a short period of time.